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library verilog; use verilog.vl_types.all; entity b5mux21 is port( mo : out vl_logic_vector(4 downto 0); a : in vl_logic_vector(4 downto 0);

library verilog; use verilog.vl_types.all; entity stratix_ram_internal is generic( operation_mode : string := "single_port"; ram_block_type : string := "M512"; mixed_po

library verilog; use verilog.vl_types.all; entity MEM is port( clk : in vl_logic; M_WriteMem : in vl_logic; M_ALUResult : in vl_logic_vecto

library verilog; use verilog.vl_types.all; entity ID is port( clk : in vl_logic; rst : in vl_logic; D_IR : in vl_logic_vector

library verilog; use verilog.vl_types.all; entity non_blocking is port( clk : in vl_logic; a : in vl_logic_vector(3 downto 0); b

library verilog; use verilog.vl_types.all; entity tb_ADPLL is generic( del : integer := 1; cnt_size : integer := 4; cycle_time : integer := 200

library verilog; use verilog.vl_types.all; entity alu_src3_sel is port( sel : in vl_logic; pc : in vl_logic_vector(7 downto 0); dptr

library verilog; use verilog.vl_types.all; entity reg8 is port( \in\ : in vl_logic_vector(7 downto 0); \out\ : out vl_logic_vector(7 downto 0);

library verilog; use verilog.vl_types.all; entity reg4 is port( \in\ : in vl_logic_vector(3 downto 0); \out\ : out vl_logic_vector(3 downto 0);

library verilog; use verilog.vl_types.all; entity reg2 is port( \in\ : in vl_logic_vector(1 downto 0); \out\ : out vl_logic_vector(1 downto 0);