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library verilog; use verilog.vl_types.all; entity cla7 is port( cout : out vl_logic_vector(6 downto 0); p : in vl_logic_vector(6 downto 0);

library verilog; use verilog.vl_types.all; entity plain_register is port( clk : in vl_logic; din : in vl_logic_vector(31 downto 0); dout

library verilog; use verilog.vl_types.all; entity clearable_register is port( clk : in vl_logic; din : in vl_logic_vector(31 downto 0); dout

library verilog; use verilog.vl_types.all; entity plain_register is port( clk : in vl_logic; din : in vl_logic_vector(31 downto 0); dout

library verilog; use verilog.vl_types.all; entity adder7 is port( s : out vl_logic_vector(6 downto 0); co : out vl_logic; a :

library verilog; use verilog.vl_types.all; entity mux7 is port( in1 : in vl_logic_vector(6 downto 0); in2 : in vl_logic_vector(6 downto 0);

library verilog; use verilog.vl_types.all; entity cla5 is port( cout : out vl_logic_vector(4 downto 0); p : in vl_logic_vector(4 downto 0);

library verilog; use verilog.vl_types.all; entity mux5 is port( in1 : in vl_logic_vector(4 downto 0); in2 : in vl_logic_vector(4 downto 0);

library verilog; use verilog.vl_types.all; entity adder4 is port( s : out vl_logic_vector(3 downto 0); co : out vl_logic; a :

library verilog; use verilog.vl_types.all; entity cla4 is port( cout : out vl_logic_vector(3 downto 0); p : in vl_logic_vector(3 downto 0);