_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity cla7 is
    port(
        cout            : out    vl_logic_vector(6 downto 0);
        p               : in     vl_logic_vector(6 downto 0);
        g               : in     vl_logic_vector(6 downto 0);
        cin             : in     vl_logic
    );
end cla7;