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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity accumulator is
port(
clk : in vl_logic;
reset : in vl_logic;
initial_phase : in vl_log
voptqqt3i4
library verilog;
use verilog.vl_types.all;
entity bldcm_con is
port(
clk : in vl_logic;
dir : in vl_logic;
hall : in vl_logic
voptwma6kk
library verilog;
use verilog.vl_types.all;
entity bldcm_con is
port(
clk : in vl_logic;
dir : in vl_logic;
hall : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bldcm_con is
port(
clk : in vl_logic;
dir : in vl_logic;
hall : in vl_logic
bldcm_con.hif
Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
38
2449
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Sta
fdiv.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity uart_51 is
generic(
idle : integer := 11;
start : integer := 0;
d0 : integer := 1;
flow_led.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
flicker_led.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************