_primary.vhd

来自「符合8051协议规范的UART的Verilog源代码.该压缩包是一个models」· VHDL 代码 · 共 36 行

library verilog;
use verilog.vl_types.all;
entity uart_51 is
    generic(
        idle            : integer := 11;
        start           : integer := 0;
        d0              : integer := 1;
        d1              : integer := 2;
        d2              : integer := 3;
        d3              : integer := 4;
        d4              : integer := 5;
        d5              : integer := 6;
        d6              : integer := 7;
        d7              : integer := 8;
        tb8_bit         : integer := 9;
        stop_bit        : integer := 10
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        wr              : in     vl_logic;
        wr_bit          : in     vl_logic;
        addr            : in     vl_logic_vector(7 downto 0);
        bit_in          : in     vl_logic;
        data_in         : in     vl_logic_vector(7 downto 0);
        t1_ow           : in     vl_logic;
        rxd             : in     vl_logic;
        txd             : out    vl_logic;
        intr            : out    vl_logic;
        data_out        : out    vl_logic_vector(7 downto 0);
        pcon            : out    vl_logic_vector(7 downto 0);
        scon            : out    vl_logic_vector(7 downto 0);
        rx_sbuf         : out    vl_logic_vector(7 downto 0)
    );
end uart_51;