代码搜索结果
找到约 10,000 项符合
Verilog 的代码
list_prim_delays_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
list_prim_delays_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 9, 1999 11:05:42
Verilog_XL_Turbo_NT 2.6.9 J
read_vecval_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
read_vecval_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 9, 1999 01:52:57
Verilog_XL_Turbo_NT 2.6.9 Jan 9
can_registers.prj
verilog work can_register_asyn_syn.v
verilog work can_register_asyn.v
verilog work can_register.v
verilog work can_registers.v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_ibo is
port(
di : in vl_logic_vector(7 downto 0);
do : out vl_logic_vector(7 downto 0)
);
s3aeval_fpga_intro_tutorial_readme_10.1.00.txt
Title: FPGA Introduction Tutorial
(Based on the Avnet Spartan-3A Evaluation kit)
Version: 10.1.00
Date: May 27, 2008
Zip File Contents:
blink_led_verilog.zip - Final ISE project for Verilog v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vga_control is
generic(
h_vidio : integer := 0;
h_front : integer := 1;
h_sync : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Add_half_0_delay is
port(
sum : out vl_logic;
c_out : out vl_logic;
a : in v
roycpld.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
state_machine.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
state_machine.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni