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Verilog 的代码
invoke_options_test.v
/**************************************************************************
* $test_invoke_options example -- Verilog test bench source code
*
* Verilog test bench to test the $test_invoke_optio
show_all_nets_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
show_all_nets_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 21:23:36
Verilog_XL_Turbo_NT 2.6.9 Nov
read_vecval_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
read_vecval_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 26, 1998 21:40:22
Verilog_XL_Turbo_NT 2.6.9 Nov 26
show_all_nets_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
show_all_nets_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998 21:23:36
Verilog_XL_Turbo_NT 2.6.9 Nov
show_all_nets_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
show_all_nets_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 28, 1998 20:43:55
Verilog_XL_Turbo_NT 2.6.9 Dec
show_all_signals1_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
show_all_signals1_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 5, 1999 04:53:15
Verilog_XL_Turbo_NT 2.6.9
port_info_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
port_info_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 6, 1999 02:07:46
Verilog_XL_Turbo_NT 2.6.9 Jan 6,
display_all_nets_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
display_all_nets_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 6, 1999 21:31:23
Verilog_XL_Turbo_NT 2.6.9 J
my_monitor_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
my_monitor_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Jan 11, 1999 14:00:45
Verilog_XL_Turbo_NT 2.6.9 Jan 11,
invoke_commands_test.v
/**************************************************************************
* $print_invoke_commands example -- Verilog test bench source code
*
* Verilog test bench to test the $print_invoke_co