port_info_test.log

pli_handbook_examples_pc verilog hdl 与C的接口的典型例子

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    port_info_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Jan  6, 1999  02:07:46
Verilog_XL_Turbo_NT 2.6.9   Jan  6, 1999  02:07:46

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Compiling source file "port_info_test.v"

Warning!  Too few module port connections                   [Verilog-TFMPC]    
          "port_info_test.v", 17: i1(a, b, ci, sum, co)
Highest level modules:
test


Module addbit:
  Instance name: test.i1
  Module type: module instance
  Ports:
    a        1-bit input     Expanded=false    Unexpanded=false
      Loconn type = accWire
      Hiconn type = accRegister

    b        1-bit input     Expanded=false    Unexpanded=false
      Loconn type = accWire
      Hiconn type = accRegister

    ci       1-bit input     Expanded=false    Unexpanded=false
      Loconn type = accWire
      Hiconn type = accRegister

    sum      1-bit output    Expanded=false    Unexpanded=false
      Loconn type = accRegister
      Hiconn type = accWire

    co       1-bit output    Expanded=false    Unexpanded=false
      Loconn type = accRegister
      Hiconn type = accWire

    foo      4-bit output    Expanded=true     Unexpanded=false
      Loconn type = accWand
      Hiconn type = none

L22 "port_info_test.v": $finish at simulation time 20
1 warning
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.9 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Jan  6, 1999  02:07:47