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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity or3_fd_v2 is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer := 1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity or_fd_v2 is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer := 1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity or3_fd_v4 is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer := 1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tb is
generic(
eeprom_address : integer := 80;
i2c_address_base: integer := 0
);
end tb;
testbench.tdo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Verilog Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module prescale_counter
vlog -93 +libext+.v+.ve+
alu_tst_wave.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Dec 19 17:46:43 中国标准时间 2002
##
vlib work
vlog -93 +libext+.v+.ve+ +define+OVI_Verilog+ ALU.V
vlog -93 +libext+.
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity \Signal\ is
port(
RESET : out vl_logic;
CLK : out vl_logic;
RD : out vl_logic;
key1.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
mem_ctrl1.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
jiaozhijiejiaozhi.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu