key1.map.qmsg

Altera CPLD矩阵键盘一个很不错的Altera芯片程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 04 16:18:45 2007 " "Info: Processing started: Sun Feb 04 16:18:45 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off key1 -c key1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key1 -c key1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file key1.v" { { "Info" "ISGN_ENTITY_NAME" "1 key1 " "Info: Found entity 1: key1" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "key1 " "Info: Elaborating entity \"key1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 key1.v(27) " "Warning (10230): Verilog HDL assignment warning at key1.v(27): truncated value with size 32 to match size of target (16)" {  } { { "key1.v" "" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 27 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_scan\[0\]~0 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_scan\[0\]~0\"" {  } { { "key1.v" "cnt_scan\[0\]~0" { Text "I:/Mars-7128-S Altera CPLD开发板/示例程序/Verilog/接口实验/矩阵键盘/key1/key1.v" 22 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:cnt_scan_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:cnt_scan_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}