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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdx_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdti_s is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_iv_dci_18 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_hstl_iv_dci is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt_s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_ramb4_s16_s16 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integ
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_lut5 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
adr0 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_lut7 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
adr0 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_lut6 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
adr0 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_lut3 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
adr0 : in