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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string
uart.log
#Build: Synplify for Lattice 8.6.2B, Build 013R, Jun 5 2006
#install: D:\PROGRAM\ISPLEVER\SYNPBASE
#OS: Windows XP 5.1
#Hostname: RYAN-XU
#Tue Jul 17 10:47:41 2007
$ Start of Compile
#Tue J
automake.err
Synplicity VHDL/Verilog HDL Synthesizer finished successfully
#Build: Synplify for Lattice 8.6.2B, Build 013R, Jun 5 2006
#install: D:\PROGRAM\ISPLEVER\SYNPBASE
#OS: Windows XP 5.1
#Hostname: R
counter_16_bits.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
main.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
pulse_16_sum.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity comp16 is
port(
o : out vl_logic;
s : out vl_logic;
a : in vl_logic_ve
counter_4_bit.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity shifter is
port(
seri_in : in vl_logic;
clk : in vl_logic;
clrb : in vl_logic;
counter_16_bits.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus