uart.log

UART 串口程序

#Build: Synplify for Lattice 8.6.2B, Build 013R, Jun  5 2006
#install: D:\PROGRAM\ISPLEVER\SYNPBASE
#OS: Windows XP 5.1
#Hostname: RYAN-XU

#Tue Jul 17 10:47:41 2007

$ Start of Compile
#Tue Jul 17 10:47:41 2007

Synplicity Verilog Compiler, version 3.7, Build 042R, built Sep 14 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\PROGRAM\ISPLEVER\SYNPBASE\lib\lucent\xp.v"
@I::"D:\program\isplever\ispcpld\..\cae_library\synthesis\verilog\XP.v"
@I::"F:\CUSTMO~1\CODETE~1\2\1\uart_v.h"
@I::"F:\CUSTMO~1\uart_verilog\txmit.v"
@I::"F:\CUSTMO~1\uart_verilog\rcvr.v"
@I::"F:\CUSTMO~1\uart_verilog\uart.v"
Verilog syntax check successful!
Selecting top level module uart
@N: CG364 :"F:\CUSTMO~1\uart_verilog\rcvr.v":23:7:23:10|Synthesizing module rcvr

@N: CG364 :"F:\CUSTMO~1\uart_verilog\txmit.v":23:7:23:11|Synthesizing module txmit

@N: CG364 :"F:\CUSTMO~1\uart_verilog\uart.v":24:7:24:10|Synthesizing module uart

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jul 17 10:47:42 2007

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Synplicity Generic Technology Mapper, Version 9.0.0, Build 273R, Built Sep 19 2006 21:00:32
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Product Version Version 8.6.2B
@N: MF249 |Running in 32-bit mode.


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)
@N:"f:\custmo~1\uart_verilog\rcvr.v":127:0:127:5|Found counter in view:work.rcvr(verilog) inst no_bits_rcvd[3:0]
@N:"f:\custmo~1\uart_verilog\txmit.v":140:0:140:5|Found counter in view:work.txmit(verilog) inst no_bits_sent[3:0]

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

Clock Buffers:
  Inserting Clock buffer on net u1.clkdiv[3], 	TNM=u1_clkdiv_3_
  Inserting Clock buffer for port clk16x,	TNM=clk16x
  Inserting Clock buffer for port wrn,	TNM=wrn


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -3.31ns		  60 /        62
   2		0h:00m:00s		    -3.31ns		  60 /        62
   3		0h:00m:00s		    -3.31ns		  60 /        62
------------------------------------------------------------

Timing driven replication report
@N: FX271 :"f:\custmo~1\uart_verilog\txmit.v":140:0:140:5|Instance "u2.no_bits_sent[0]" with 13 loads has been replicated 2 time(s) to improve timing 
@N: FX271 :"f:\custmo~1\uart_verilog\txmit.v":140:0:140:5|Instance "u2.no_bits_sent[2]" with 12 loads has been replicated 2 time(s) to improve timing 
@N: FX271 :"f:\custmo~1\uart_verilog\txmit.v":140:0:140:5|Instance "u2.no_bits_sent[3]" with 11 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"f:\custmo~1\uart_verilog\txmit.v":140:0:140:5|Instance "u2.no_bits_sent[1]" with 11 loads has been replicated 1 time(s) to improve timing 
Added 6 Registers via timing driven replication
Added 6 LUTs via timing driven replication

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -2.12ns		  67 /        68
   2		0h:00m:01s		    -2.12ns		  67 /        68
   3		0h:00m:01s		    -2.12ns		  67 /        68
Timing driven replication report
No replication required.

   4		0h:00m:01s		    -2.12ns		  67 /        68
   5		0h:00m:01s		    -2.12ns		  67 /        68
   6		0h:00m:01s		    -2.12ns		  67 /        68
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.12ns		  67 /        68
   2		0h:00m:01s		    -2.12ns		  67 /        68
   3		0h:00m:01s		    -2.12ns		  67 /        68
Timing driven replication report
No replication required.

   4		0h:00m:01s		    -2.12ns		  67 /        68
   5		0h:00m:01s		    -2.12ns		  67 /        68
   6		0h:00m:01s		    -2.12ns		  67 /        68
------------------------------------------------------------

Net buffering Report for view:work.uart(verilog):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB)
Found clock uart|clk16x with period 5.00ns 
Found clock uart|wrn with period 5.00ns 
Found clock rcvr|clkdiv_inferred_clock[3] with period 5.00ns 
Found clock txmit|clkdiv_inferred_clock[3] with period 5.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jul 17 10:47:46 2007
#


Top view:               uart
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: -2.986

                                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock                     Frequency     Frequency     Period        Period        Slack      Type         Group              
--------------------------------------------------------------------------------------------------------------------------------------
rcvr|clkdiv_inferred_clock[3]      200.0 MHz     203.8 MHz     5.000         4.907         0.093      inferred     Inferred_clkgroup_1
txmit|clkdiv_inferred_clock[3]     200.0 MHz     91.1 MHz      5.000         10.972        -2.986     inferred     Inferred_clkgroup_3
uart|clk16x                        200.0 MHz     203.8 MHz     5.000         4.907         0.093      inferred     Inferred_clkgroup_0
uart|wrn                           200.0 MHz     397.9 MHz     5.000         2.513         2.487      inferred     Inferred_clkgroup_2
System                             200.0 MHz     169.2 MHz     5.000         5.909         -0.909     system       default_clkgroup   
======================================================================================================================================





Clock Relationships
*******************

Clocks                                                          |    rise  to  rise   |    fall  to  fall    |    rise  to  fall    |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                        Ending                          |  constraint  slack  |  constraint  slack   |  constraint  slack   |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------------
uart|clk16x                     uart|clk16x                     |  5.000       0.093  |  No paths    -       |  No paths    -       |  No paths    -    
uart|clk16x                     rcvr|clkdiv_inferred_clock[3]   |  Diff grp    -      |  No paths    -       |  No paths    -       |  No paths    -    
rcvr|clkdiv_inferred_clock[3]   uart|clk16x                     |  Diff grp    -      |  No paths    -       |  No paths    -       |  No paths    -    
rcvr|clkdiv_inferred_clock[3]   rcvr|clkdiv_inferred_clock[3]   |  5.000       0.093  |  No paths    -       |  No paths    -       |  No paths    -    
uart|wrn                        uart|wrn                        |  No paths    -      |  5.000       2.487   |  No paths    -       |  No paths    -    
uart|wrn                        txmit|clkdiv_inferred_clock[3]  |  No paths    -      |  Diff grp    -       |  No paths    -       |  No paths    -    
txmit|clkdiv_inferred_clock[3]  uart|clk16x                     |  Diff grp    -      |  No paths    -       |  No paths    -       |  No paths    -    
txmit|clkdiv_inferred_clock[3]  txmit|clkdiv_inferred_clock[3]  |  5.000       1.886  |  5.000       -0.330  |  2.500       -2.986  |  No paths    -    
========================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port       Starting            User           Arrival     Required          
Name       Reference           Constraint     Time        Time         Slack
           Clock                                                            
----------------------------------------------------------------------------
clk16x     NA                  NA             NA          NA           NA   
din[0]     System (rising)     NA             0.000       2.487             
din[1]     System (rising)     NA             0.000       2.487             
din[2]     System (rising)     NA             0.000       2.487             
din[3]     System (rising)     NA             0.000       2.487             
din[4]     System (rising)     NA             0.000       2.487             
din[5]     System (rising)     NA             0.000       2.487             
din[6]     System (rising)     NA             0.000       2.487             
din[7]     System (rising)     NA             0.000       2.487             
rdn        System (rising)     NA             0.000       -0.909            
rst        System (rising)     NA             0.000       1.072             
rxd        System (rising)     NA             0.000       2.487             
wrn        System (rising)     NA             0.000       2.379             
============================================================================


Output Ports: 

Port              Starting                                     User           Arrival     Required          
Name              Reference                                    Constraint     Time        Time         Slack
                  Clock                                                                                     
------------------------------------------------------------------------------------------------------------
data_ready        uart|clk16x (rising)                         NA             4.907       5.000             
dout[0]           System (rising)                              NA             5.909       5.000             
dout[1]           System (rising)                              NA             5.909       5.000             
dout[2]           System (rising)                              NA             5.909       5.000             
dout[3]           System (rising)                              NA             5.909       5.000             
dout[4]           System (rising)                              NA             5.909       5.000             
dout[5]           System (rising)                              NA             5.909       5.000             
dout[6]           System (rising)                              NA             5.909       5.000             
dout[7]           System (rising)                              NA             5.909       5.000             
framing_error     rcvr|clkdiv_inferred_clock[3] (rising)       NA             4.847       5.000             
parity_error      rcvr|clkdiv_inferred_clock[3] (rising)       NA             4.907       5.000             
sdo               txmit|clkdiv_inferred_clock[3] (falling)     NA             4.847       5.000             
tbre              uart|clk16x (rising)                         NA             4.847       5.000             
tsre              txmit|clkdiv_inferred_clock[3] (falling)     NA             4.847       5.000             
============================================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lfxp3c-3

Register bits: 68 of 3072 (2%)
I/O cells:       27

Details:
FD1P3AX:        18
FD1P3AY:        2
FD1S3AX:        9
FD1S3AY:        3
FD1S3DX:        15
GSR:            1
IB:             13
IFS1P3BX:       1
IFS1P3DX:       8
INV:            7
OB:             6
OBZ:            8
OFS1P3BX:       2
OFS1P3DX:       10
ORCALUT4:       61
VHI:            1
VLO:            1

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 58MB)
Writing Analyst data base F:\CUSTMO~1\CODETE~1\2\1\uart.srm
@N: MF203 |Set autoconstraint_io 
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io 
Version 8.6.2B
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io 
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io 
@N: MF203 |Set autoconstraint_io 
Mapper successful!
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
# Tue Jul 17 10:47:47 2007

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