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library verilog; use verilog.vl_types.all; entity hcstratix_mac_mult is generic( dataa_width : integer := 18; datab_width : integer := 18; dataa_clock : string

library verilog; use verilog.vl_types.all; entity b_shift1 is generic( bwidth : integer := 32 ); port( b1_out : out vl_logic_vector; b1_in

library verilog; use verilog.vl_types.all; entity b_shift3 is generic( bwidth : integer := 32 ); port( b3_out : out vl_logic_vector; b3_in

library verilog; use verilog.vl_types.all; entity bk_shift2 is generic( bwidth : integer := 32 ); port( b2_out : out vl_logic_vector; b2_in

library verilog; use verilog.vl_types.all; entity b_shift2 is generic( bwidth : integer := 32 ); port( b2_out : out vl_logic_vector; b2_in

library verilog; use verilog.vl_types.all; entity b_shift0 is generic( bwidth : integer := 32 ); port( b0_out : out vl_logic_vector; b0_in

library verilog; use verilog.vl_types.all; entity bk_shift0 is generic( bwidth : integer := 32 ); port( b0_out : out vl_logic_vector; b0_in

library verilog; use verilog.vl_types.all; entity bk_shift1 is generic( bwidth : integer := 32 ); port( b1_out : out vl_logic_vector; b1_in

library verilog; use verilog.vl_types.all; entity b_shift4 is generic( bwidth : integer := 32 ); port( b4_out : out vl_logic_vector; b4_in

library verilog; use verilog.vl_types.all; entity stratixgx_crcblock is generic( oscillator_divider: integer := 1 ); port( clk : in vl_logic; shiftn