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Verilog 的代码
time_cnt_tb.tbw
version 3
C:/examples/wtut_ver/wtut_ver_completed/time_cnt.v
time_cnt
VERILOG
VERILOG
C:/examples/wtut_ver/wtut_ver_completed/time_cnt_tb.xwv
Clocked
-
-
3000000000
ns
GSR:true
PRLD:false
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20ke_lcell is
generic(
operation_mode : string := "normal";
output_mode : string := "reg_and_comb";
packed_mode
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_crcblock is
generic(
oscillator_divider: integer := 1
);
port(
clk : in vl_logic;
shiftnld
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_deskew_fifo is
generic(
a : integer := 195;
\FIFO_DEPTH\ : integer := 16
);
port(
datai
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_reset_block is
port(
txdigitalreset : in vl_logic_vector(3 downto 0);
rxdigitalreset : in vl_logic_vector(3 do
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_hssi_transmitter is
generic(
channel_num : integer := 1;
channel_width : integer := 8;
serialization_facto
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity flex6k_lcell is
generic(
operation_mode : string := "normal";
output_mode : string := "reg_and_comb";
packed_mode
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vmax_asynch_io
IIOUS66D8J>U;1_Acl?^a]0
V_H]lFjiZ_4FDWD=Ak1
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/max_atoms.v)
L0 32
OV
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20k_lcell is
generic(
operation_mode : string := "normal";
output_mode : string := "reg_and_comb";
packed_mode