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#-- Synplicity, Inc. #-- Version 7.2.1 #-- Project file D:\project\CardBus\Source\verilog\cardbus_5632.prj #-- Written on Wed Apr 07 21:51:57 2004 #add_file options add_file -verilog "c

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

verilog work can_register_asyn_syn.v verilog work can_register_asyn.v verilog work can_register.v verilog work can_registers.v

library verilog; use verilog.vl_types.all; entity can_ibo is port( di : in vl_logic_vector(7 downto 0); do : out vl_logic_vector(7 downto 0) );

library verilog; use verilog.vl_types.all; entity fft64_tbw_v is generic( VCC : integer := 1; GND : integer := 0; FFT_DOT_NUM : integer := 64;

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

library verilog; use verilog.vl_types.all; entity clk_contrl is port( clk_5m : in vl_logic; rst : in vl_logic; clk_2_5m : out vl_logi

library verilog; use verilog.vl_types.all; entity back is port( clk_5m : in vl_logic; rst : in vl_logic; nd_a : in vl_logic;

version 3 d:\lijunyang_software\code_chinaeda\pingpang\pingpang.v pingpang VERILOG VERILOG test.xwv Clocked - - 100000000000 ns GSR:false PRLD:false 100000000 CLOCK_LIST_BEGIN clk_5m 1