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Verilog 的代码
gw.prj
verilog work "../complexmul.v"
verilog work "../cutbit/jiewei.v"
verilog work "eexy.v"
verilog work "muxe.v"
verilog work "gw.v"
ppl.prj
verilog work "clkf.v"
verilog work "send1.v"
verilog work "send2.v"
verilog work "comp.v"
verilog work "ppl.v"
ppl.prj
verilog work "clkf.v"
verilog work "send1.v"
verilog work "send2.v"
verilog work "comp.v"
verilog work "ppl.v"
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity KeypadScan is
port(
clk : in vl_logic;
\out\ : out vl_logic_vector(5 downto 0);
row
can_registers.prj
verilog work can_register_asyn_syn.v
verilog work can_register_asyn.v
verilog work can_register.v
verilog work can_registers.v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_ibo is
port(
di : in vl_logic_vector(7 downto 0);
do : out vl_logic_vector(7 downto 0)
);
division_a.hif
Version 7.1 Build 156 04/30/2007 SJ Full Version
7
2401
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
cic.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
testbench.txt
writting testbench
入门级的还有XILINX的一篇文档how to write a testbench。
你看看这个，看思想。
如果说要看书的话，当然是“writting testbench”，是一本好书大书，英文的，要慢慢看。入门级的还有XILINX的一篇文档how to write a testbench。
主要是看看思想，本论坛中有好几篇不错的文章。你看看。
下面
protect.rpt
Project Informationc:\software\project_beijing\cpld_v1.1\pwm_verilog hdl_v1.1\protect.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 03/06/2006 17:15:12
Copyright (C) 1