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Verilog 的代码
ddr_command.versim_xlate
ddr_command.versim_xlate -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
ddr_command.versim_par
ddr_command.versim_par -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
fcout.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
mo : out vl_logic_vector(15 downto 0);
a : in vl_logic_vector(15 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
mo : out vl_logic_vector(16 downto 0);
a : in vl_logic_vector(16 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity leg_icache is
generic(
IDLE : integer := 1;
HIT_DETECT : integer := 2;
RELOAD_1 : integer := 4;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity leg_dcache is
generic(
IDLE : integer := 1;
HIT_DETECT : integer := 2;
RELOAD_1 : integer := 4;