代码搜索结果
找到约 10,000 项符合
Verilog 的代码
usrt_receive.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
uart_top.sim.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
bidir.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
38
2265
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
diff_io_top.fld
E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db
Diff_io_top
JWU
V1
diff_io_top.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity add8 is
generic(
S1 : integer := 8;
S0 : integer := 4
);
port(
a : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sum4 is
port(
a : in vl_logic_vector(3 downto 0);
b : in vl_logic_vector(3 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity firfilter_1 is
port(
clock : in vl_logic;
reset : in vl_logic;
x : in vl_log
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iir_6_filter is
port(
din : in vl_logic_vector(17 downto 0);
dout : out vl_logic_vector(17 downto 0)
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fir_160_tap is
port(
din : in vl_logic_vector(11 downto 0);
dout : out vl_logic_vector(31 downto 0);