uart_top.sim.qmsg

Uart port 是一段不错的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 12 15:23:21 2006 " "Info: Processing started: Tue Dec 12 15:23:21 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off uart_top -c uart_top " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off uart_top -c uart_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "uart_emitter:uart_emitter\|bus_reg\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"uart_emitter:uart_emitter\|bus_reg\[7\]\" in design." {  } { { "E:/verilog/uart/uart_top.vwf" "" { Waveform "E:/verilog/uart/uart_top.vwf" "uart_emitter:uart_emitter\|bus_reg\[7\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "uart_emitter:uart_emitter\|bus_reg\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"uart_emitter:uart_emitter\|bus_reg\[6\]\" in design." {  } { { "E:/verilog/uart/uart_top.vwf" "" { Waveform "E:/verilog/uart/uart_top.vwf" "uart_emitter:uart_emitter\|bus_reg\[6\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "uart_emitter:uart_emitter\|bus_reg\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"uart_emitter:uart_emitter\|bus_reg\[5\]\" in design." {  } { { "E:/verilog/uart/uart_top.vwf" "" { Waveform "E:/verilog/uart/uart_top.vwf" "uart_emitter:uart_emitter\|bus_reg\[5\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "uart_emitter:uart_emitter\|bus_reg\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"uart_emitter:uart_emitter\|bus_reg\[4\]\" in design." {  } { { "E:/verilog/uart/uart_top.vwf" "" { Waveform "E:/verilog/uart/uart_top.vwf" "uart_emitter:uart_emitter\|bus_reg\[4\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "uart_emitter:uart_emitter\|bus_reg\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"uart_emitter:uart_emitter\|bus_reg\[3\]\" in design." {  } { { "E:/verilog/uart/uart_top.vwf" "" { Waveform "E:/verilog/uart/uart_top.vwf" "uart_emitter:uart_emitter\|bus_reg\[3\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "uart_emitter:uart_emitter\|bus_reg\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"uart_emitter:uart_emitter\|bus_reg\[2\]\" in design." {  } { { "E:/verilog/uart/uart_top.vwf" "" { Waveform "E:/verilog/uart/uart_top.vwf" "uart_emitter:uart_emitter\|bus_reg\[2\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "uart_emitter:uart_emitter\|bus_reg\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"uart_emitter:uart_emitter\|bus_reg\[1\]\" in design." {  } { { "E:/verilog/uart/uart_top.vwf" "" { Waveform "E:/verilog/uart/uart_top.vwf" "uart_emitter:uart_emitter\|bus_reg\[1\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "uart_emitter:uart_emitter\|bus_reg\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"uart_emitter:uart_emitter\|bus_reg\[0\]\" in design." {  } { { "E:/verilog/uart/uart_top.vwf" "" { Waveform "E:/verilog/uart/uart_top.vwf" "uart_emitter:uart_emitter\|bus_reg\[0\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     61.40 % " "Info: Simulation coverage is      61.40 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "2009577 " "Info: Number of transitions in simulation is 2009577" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 8 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 12 15:25:59 2006 " "Info: Processing ended: Tue Dec 12 15:25:59 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:02:40 " "Info: Elapsed time: 00:02:40" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}