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library verilog; use verilog.vl_types.all; entity x_inv is port( o : out vl_logic; i : in vl_logic ); end x_inv;

library verilog; use verilog.vl_types.all; entity x_one is port( o : out vl_logic ); end x_one;

library verilog; use verilog.vl_types.all; entity x_ramb16_s4_s4 is generic( cds_action : string := "ignore"; init_a : integer := 0; init_b : intege

library verilog; use verilog.vl_types.all; entity x_pd is port( o : out vl_logic ); end x_pd;

library verilog; use verilog.vl_types.all; entity x_ipad is port( pad : in vl_logic ); end x_ipad;

library verilog; use verilog.vl_types.all; entity x_ramb16_s1_s1 is generic( cds_action : string := "ignore"; init_a : integer := 0; init_b : intege

library verilog; use verilog.vl_types.all; entity x_bpad is port( pad : inout vl_logic ); end x_bpad;

library verilog; use verilog.vl_types.all; entity x_zero is port( o : out vl_logic ); end x_zero;

library verilog; use verilog.vl_types.all; entity or_a_b is port( a_in : in vl_logic; b_in : in vl_logic; or_out : out vl_logic

library verilog; use verilog.vl_types.all; entity vfft32_fft4_32_v2_0 is generic( b : integer := 16 ); port( clk : in vl_logic; reset