_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_fft4_32_v2_0 is
    generic(
        b               : integer := 16
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        ce              : in     vl_logic;
        conj            : in     vl_logic;
        scale_rank3_by  : in     vl_logic_vector(1 downto 0);
        scale_rank4_by  : in     vl_logic_vector(1 downto 0);
        x0r             : in     vl_logic_vector;
        x0i             : in     vl_logic_vector;
        x1r             : in     vl_logic_vector;
        x1i             : in     vl_logic_vector;
        x2r             : in     vl_logic_vector;
        x2i             : in     vl_logic_vector;
        x3r             : in     vl_logic_vector;
        x3i             : in     vl_logic_vector;
        y0r             : out    vl_logic_vector;
        y0i             : out    vl_logic_vector;
        y1r             : out    vl_logic_vector;
        y1i             : out    vl_logic_vector;
        y2r             : out    vl_logic_vector;
        y2i             : out    vl_logic_vector;
        y3r             : out    vl_logic_vector;
        y3i             : out    vl_logic_vector
    );
end vfft32_fft4_32_v2_0;