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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufs_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos33_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_27 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnd_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_31 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvttl_s_16 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vcc is
generic(
cds_action : string := "ignore"
);
port(
p : out vl_logic
);
end vcc;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_35 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s2 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_24 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1