代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_gtl_dci is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_07 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s1_s18 is
generic(
cds_action : string := "ignore";
init_a : integer := 0;
init_b : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bufe is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_s_12 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1_s4 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufen is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufndn_f_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_14 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1