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找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dff is
generic(
cardinality : integer := 1
);
port(
d : in vl_logic_vector;
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pa_se is
port(
clk : in vl_logic_vector(0 downto 0);
\in\ : in vl_logic_vector(3 downto 0);
people4.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file peop
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity time_tst is
generic(
PERIOD : integer := 40;
DUTY_CYCLE : real := 0.500000;
OFFSET : integer :=
isim.hdlsourcefiles
J:/I.31/rtf/verilog/src/simprims/X_ZERO.v
J:/I.31/rtf/verilog/src/simprims/X_CKBUF.v
J:/I.31/rtf/verilog/src/simprims/X_SFF.v
J:/I.31/rtf/verilog/src/simprims/X_INV.v
J:/I.31/rtf/verilog/src/simpr