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找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
d__program_fpga_software_modelsim_xilinx_lib_unimacro_ver__info
m255
13
cModel Technology
dC:\Documents and Settings\user
vBRAM_SDP_MACRO
I]Wf[`HE_eHA2WFo2hIfCJ0
VXI9dGS?DBFdBNBK@O]lO01
dC:\Documents and Settings\user
w1202685733
FD:\Program\FPGA_software\ISE10.
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
counter4x5.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity QPSKenckde is
port(
clk : in vl_logic;
reset : in vl_logic;
bit_in : in vl_logi
lcd.hif
Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Sta
traffic.hif
Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Sta
arm.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
27
1589
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Pat
pulse_16_sum.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
led8bit.hif
Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
39
2306
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- St