📄 d__program_fpga_software_modelsim_xilinx_lib_unimacro_ver__info
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m25513cModel Technology
dC:\Documents and Settings\user
vBRAM_SDP_MACROI]Wf[`HE_eHA2WFo2hIfCJ0VXI9dGS?DBFdBNBK@O]lO01dC:\Documents and Settings\userw1202685733FD:\Program\FPGA_software\ISE10.1\ISE\verilog\src\unimacro\BRAM_SDP_MACRO.vL0 29VXI9dGS?DBFdBNBK@O]lO01OE;L;6.2b;35r131o-work D:\Program\FPGA_software\ModelSim\xilinx_lib\unimacro_vern@b@r@a@m_@s@d@p_@m@a@c@r@ovBRAM_SINGLE_MACROIeNe?H]?i;>VH[;H@1iWX22VkS^8Ufz77QXIEcX8hV:_z1dC:\Documents and Settings\userw1206641911FD:\Program\FPGA_software\ISE10.1\ISE\verilog\src\unimacro\BRAM_SINGLE_MACRO.vL0 30VkS^8Ufz77QXIEcX8hV:_z1OE;L;6.2b;35r131o-work D:\Program\FPGA_software\ModelSim\xilinx_lib\unimacro_vern@b@r@a@m_@s@i@n@g@l@e_@m@a@c@r@ovBRAM_TDP_MACROITedPzFeFKil34kO@N@16?3V;MS5R5d>Fkh7A4kG?NOZG1dC:\Documents and Settings\userw1202685733FD:\Program\FPGA_software\ISE10.1\ISE\verilog\src\unimacro\BRAM_TDP_MACRO.vL0 29V;MS5R5d>Fkh7A4kG?NOZG1OE;L;6.2b;35r131o-work D:\Program\FPGA_software\ModelSim\xilinx_lib\unimacro_vern@b@r@a@m_@t@d@p_@m@a@c@r@ovFIFO_DUALCLOCK_MACROIVVoei:1WCZD;:@=6J`4?_0Vd_IK:>HSi952QJ6Ri1V1=3dC:\Documents and Settings\userw1206641889FD:\Program\FPGA_software\ISE10.1\ISE\verilog\src\unimacro\FIFO_DUALCLOCK_MACRO.vL0 29Vd_IK:>HSi952QJ6Ri1V1=3OE;L;6.2b;35r131o-work D:\Program\FPGA_software\ModelSim\xilinx_lib\unimacro_vern@f@i@f@o_@d@u@a@l@c@l@o@c@k_@m@a@c@r@ovFIFO_SYNC_MACROIA@]H@HkPPThgUn5FYR@>B2V;K8L>1NSjWA]eJ=XKSJSK2dC:\Documents and Settings\userw1202685736FD:\Program\FPGA_software\ISE10.1\ISE\verilog\src\unimacro\FIFO_SYNC_MACRO.vL0 28V;K8L>1NSjWA]eJ=XKSJSK2OE;L;6.2b;35r131o-work D:\Program\FPGA_software\ModelSim\xilinx_lib\unimacro_vern@f@i@f@o_@s@y@n@c_@m@a@c@r@o⌨️ 快捷键说明
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