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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mercury_io is
generic(
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output: strin
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b32mux21 is
port(
\MO\ : out vl_logic_vector(31 downto 0);
\A\ : in vl_logic_vector(31 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_tri is
port(
datain : in vl_logic;
dataout : out vl_logic;
oe : in vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b17mux21 is
port(
\MO\ : out vl_logic_vector(16 downto 0);
\A\ : in vl_logic_vector(16 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_ram_clear is
port(
aclr : in vl_logic;
d : in vl_logic;
q : out
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo