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twice.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
freq2_2.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
frequency_divider.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20ke_upcore is
generic(
processor : string := "ARM";
source : string := "";
sdram_width : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell is
generic(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bmux21 is
port(
\MO\ : out vl_logic_vector(15 downto 0);
\A\ : in vl_logic_vector(15 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_jtag is
port(
tms : in vl_logic;
tck : in vl_logic;
tdi : in vl_lo