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Verilog 的代码
default_compile.do
edfcomp "$DSN/src/fd16d.bde"
edfcomp "$DSN/src/c4u.bde"
edfcomp "$DSN/src/c4ud.bde"
edfcomp "$DSN/src/fifod.bde"
edfcomp "$DSN/src/rm16x32.bde"
edfcomp "$DSN/src/rm16x16.bde"
edfcomp "$DSN/src/f
traffic.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
38
2468
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
ps2.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
mux.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
i2c_sl~2.sty
[Normal]
synlibXRef=lc4k_vlg, Verilog.TASKLSVlog, 0, Yes
_vlog_std_v2001=lc4k_vlg, Verilog.TASKLSVlog, 0, True
[STRATEGY-LIST]
Normal=True, 1125078904
[TOUCHED-REPORT]
Design.bl2File=1125087229