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library verilog; use verilog.vl_types.all; entity mux2 is generic( WIDTH : integer := 8 ); port( data0 : in vl_logic_vector; data1

library verilog; use verilog.vl_types.all; entity pc is port( clk : in vl_logic; reset : in vl_logic; pcwrite : in vl_logic;

library verilog; use verilog.vl_types.all; entity InsMem is port( clk : in vl_logic; A : in vl_logic_vector(5 downto 0); RD :

library verilog; use verilog.vl_types.all; entity Mem is port( clk : in vl_logic; we : in vl_logic; irwrite : in vl_logic;

library verilog; use verilog.vl_types.all; entity ALU is port( clk : in vl_logic; srca : in vl_logic_vector(31 downto 0); srcb : i

library verilog; use verilog.vl_types.all; entity DataMem is port( clk : in vl_logic; we : in vl_logic; a : in vl_logic_v

library verilog; use verilog.vl_types.all; entity signExt is port( a : in vl_logic_vector(15 downto 0); signExt : in vl_logic; y

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

Version 7.2 Build 151 09/26/2007 SJ Web Edition 7 2631 OFF OFF OFF OFF ON ON ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths

.\src\fd16d.bde .\src\c4u.bde .\src\c4ud.bde .\src\fifod.bde .\src\rm16x32.bde .\src\rm16x16.bde .\src\fifo.bde .\src\TB_verilog\fifo_TB.v .\src\TB_vhd\fifo_TB.vhd