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Verilog 的代码
basketball.hif
Version 8.1 Build 163 10/28/2008 SJ Full Version
11
915
OFF
OFF
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ON
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ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
vga_dis.hif
Version 7.0 Build 33 02/05/2007 SJ Full Version
36
1980
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
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--
fcout.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
basegate.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
945
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ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
keyled.hif
Version 8.0 Build 215 05/29/2008 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
myled.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity regfile is
port(
clk : in vl_logic;
we3 : in vl_logic;
ra1 : in vl_logic_v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top_tb is
generic(
CLK_CYCLE : integer := 50
);
end top_tb;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity flopr is
port(
clk : in vl_logic;
reset : in vl_logic;
pcwrite : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
port(
clk : in vl_logic;
reset : in vl_logic;
pc : out vl_logic_vecto