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Verilog 的代码
case3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
fir_srg.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: fir_srg.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**************************************************
case3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
fir_srg.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: fir_srg.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
xianshi.hif
Version 7.0 Build 33 02/05/2007 SJ Web Edition
18
1000
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
test.hif
Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
39
2401
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- St
first.hif
Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
39
2309
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- St
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity regs is
port(
clk : in vl_logic;
reset : in vl_logic;
we : in vl_logic;