_primary.vhd

来自「用Verilog 编写的8位risc cpu」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity regs is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        we              : in     vl_logic;
        re              : in     vl_logic;
        bank            : in     vl_logic_vector(1 downto 0);
        location        : in     vl_logic_vector(4 downto 0);
        din             : in     vl_logic_vector(7 downto 0);
        dout            : out    vl_logic_vector(7 downto 0)
    );
end regs;