代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/377687/9264785
v case3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
www.eeworm.com/read/377687/9264801
v fir_srg.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: fir_srg.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
www.eeworm.com/read/377687/9264822
v lfsr.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**************************************************
www.eeworm.com/read/377687/9264838
v case3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
www.eeworm.com/read/377687/9264899
v fir_srg.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: fir_srg.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
www.eeworm.com/read/376770/9307009
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity MULTP is
port(
aclr : in vl_logic;
clken : in vl_logic;
clock : in vl_logic;
www.eeworm.com/read/374782/9384962
hif period_led.hif
Version 7.0 Build 33 02/05/2007 SJ Full Version
35
1941
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
--
www.eeworm.com/read/178219/9413683
qsf clock.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/176099/9516654
makefile
# $Id: Makefile,v 1.1.1.1 2005/01/04 02:05:54 arif_endro Exp $
#
all:
# $(MAKE) -C source fm ;
$(MAKE) -C source fm_v;
export: all
# mv -v source/*.vhd export/vhd/;
# cp -v source/modelsim_vhd.do
www.eeworm.com/read/175203/9555637
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity xcv is
generic(
IDIE : integer := 0;
A : integer := 1;
B : integer := 2;
C