代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/224583/14582554
chm (prentice) verilog hdl--guide to digital design & synthesis (2nd.ed.).chm
www.eeworm.com/read/14363/331041
chm (prentice) verilog hdl--guide to digital design & synthesis (2nd.ed.).chm
www.eeworm.com/read/17615/742847
pdf 基于verilog_hdl的uart串行通讯模块设计及仿真.pdf
www.eeworm.com/read/17677/753725
doc 第 6讲 用verilog.做cpld的设计doc.doc
www.eeworm.com/read/414379/11116941
doc 通用串行异步收发器8251的verilog hdl源代码.doc
www.eeworm.com/read/235018/14088760
pdf 用verilog hdl语言实现并串串并接口的转换.pdf
www.eeworm.com/read/349103/10851994
scr read.scr
read -format verilog verilog/new/ALARM_BLOCK.v
read -format verilog verilog/new/ALARM_SM_2.v
read -format verilog verilog/new/CLOCK_GEN.v
read -format verilog verilog/new/COMPARATOR.v
read -format ver
www.eeworm.com/read/292145/8374825
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
www.eeworm.com/read/390516/8461787
_info
m255
13
cModel Technology
dC:\Modeltech_6.1d\examples
vseqdet
IGDOGWId@JfV`ma]bRfGa@0
V7dSHhg8X?4jVXgBZJ16Ic2
dD:\verilog_test\seqdet
w1188206446
FD:/verilog_test/seqdet/sequence.v
L0 1
V7dSHhg8X?4jVX