代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/172784/9690562
v sci_alu_synchronized_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690563
v sci_alu_latched_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690657
log read_stimulus_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
read_stimulus_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 3, 1998 10:04:19
Verilog_XL_Turbo_NT 2.6.9 Dec
www.eeworm.com/read/172784/9690711
v sci_alu_synchronized_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690719
v sci_alu_latched_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690751
v sci_alu_with_delays_shell.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL shell module
*
* Scientific ALU C model, combinational logic version with pin-to-
www.eeworm.com/read/172784/9690761
log pow_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
pow_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 22, 1998 20:52:59
Verilog_XL_Turbo_NT 2.6.9 Dec 22, 1998
www.eeworm.com/read/172784/9690790
v sci_alu_synchronized_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690792
v sci_alu_latched_test.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL test bench.
*
* Verilog test bench to test the $scientific_alu C model PLI
* a
www.eeworm.com/read/172784/9690813
v sci_alu_with_delays_shell.v
/**********************************************************************
* $scientific_alu example -- Verilog HDL shell module
*
* Scientific ALU C model, combinational logic version with pin-to-