pow_test.log

来自「pli_handbook_examples_pc verilog hdl 与C」· LOG 代码 · 共 54 行

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    pow_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Dec 22, 1998  20:52:59
Verilog_XL_Turbo_NT 2.6.9   Dec 22, 1998  20:52:59

Copyright (c) 1995 Cadence Design Systems, Inc.  All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.

Copyright (c) 1995 UNIX Systems Laboratories, Inc.  Reproduced with Permission.

THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC.  USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.

                Cadence Design Systems, Inc.
                555 River Oaks Parkway
                San Jose, California  95134

For technical assistance please contact the Cadence Response Center at
1-800-CADENC2 or send email to [e-mail]

For more information on Cadence's Verilog-XL product line send email to
[e-mail]

Compiling source file "pow_test.v"
Highest level modules:
test


$pow PLI application is being used.


$pow PLI application is being used.

$pow(2,3) returns          8
$pow(a,b) returns          1 (a=1 b=0)
L35 "pow_test.v": $stop at simulation time 4
Type ? for help
C1 > $finish;
C1: $finish at simulation time 4
0 simulation events (use +profile or +listcounts option to count) + 2 accelerated events
CPU time: 0.7 secs to compile + 0.0 secs to link + 13.5 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Dec 22, 1998  20:53:13