代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5586040
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_srlc16e is
generic(
init : integer := 0
);
port(
q : out vl_logic;
q15 :
www.eeworm.com/read/159314/5586046
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_mux2 is
port(
o : out vl_logic;
ia : in vl_logic;
ib : in vl_logic;
www.eeworm.com/read/159314/5586055
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_rams128 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i :
www.eeworm.com/read/159314/5586056
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_tri is
port(
o : out vl_logic;
i : in vl_logic;
ctl : in vl_logic
www.eeworm.com/read/159314/5586059
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor2 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic
www.eeworm.com/read/159314/5586069
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_xor4 is
port(
o : out vl_logic;
i0 : in vl_logic;
i1 : in vl_logic;
www.eeworm.com/read/159314/5586072
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_suh is
port(
i : in vl_logic;
clk : in vl_logic;
ce : in vl_logic
www.eeworm.com/read/159314/5586284
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or3_fd is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer := 1
);
www.eeworm.com/read/154098/5642243
srd top.srd
f "noname"; #file 0
f "j:\example-8-1\modular_design\syn_top\virtex2.v"; #file 1
f "j:\example-8-1\modular_design\syn_top\top.v"; #file 2
VNAME 'work.module_c.verilog'; # view id 0
VNAME 'work.mod
www.eeworm.com/read/154076/5643133
crp coregen.crp
NEWPROJECT j:\projects\ise\arch_wzd_demo
SETPROJECT j:\projects\ise\arch_wzd_demo
SET BusFormat = BusFormatAngleBracket
SET XilinxFamily = Virtex2P
SET FlowVendor = Foundation_iSE
SET DesignFlow