代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585670
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity bscan is
generic(
cds_action : string := "ignore"
);
port(
drck : out vl_logic;
idle
www.eeworm.com/read/159314/5585678
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram32x1s is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585683
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_s_2 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585694
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ilflx_1f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585703
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvds is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585704
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdse is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
www.eeworm.com/read/159314/5585709
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_lvcmos25_f_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in
www.eeworm.com/read/159314/5585718
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or3b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585721
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lde is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q : o
www.eeworm.com/read/159314/5585725
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity muxf8 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0