代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585478
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnn_s_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_lo
www.eeworm.com/read/159314/5585479
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_f_6 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585482
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_pcix is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585487
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity xnor5 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585488
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fddrcpe is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585494
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdx is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
www.eeworm.com/read/159314/5585499
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_n_24 is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
www.eeworm.com/read/159314/5585500
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram16x4s is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
www.eeworm.com/read/159314/5585503
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity omux2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
d0
www.eeworm.com/read/159314/5585508
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdr_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :