代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/159314/5585424
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand3 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585433
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildx_1m is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
www.eeworm.com/read/159314/5585436
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hmap is
generic(
cds_action : string := "ignore"
);
port(
i1 : in vl_logic;
i2
www.eeworm.com/read/159314/5585438
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut4 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i0 : in
www.eeworm.com/read/159314/5585450
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o :
www.eeworm.com/read/159314/5585454
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or4b1 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585462
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobuf_ctt is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
www.eeworm.com/read/159314/5585466
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity or2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
www.eeworm.com/read/159314/5585473
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity rom32x1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
www.eeworm.com/read/159314/5585475
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdcp_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q