_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity hmap is
    generic(
        cds_action      : string  := "ignore"
    );
    port(
        i1              : in     vl_logic;
        i2              : in     vl_logic;
        i3              : in     vl_logic;
        o               : in     vl_logic
    );
end hmap;