代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/152702/12092071
srr st_mult1.srr
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Fri Mar 17 22:06:30 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synp
www.eeworm.com/read/151963/12156345
qmsg phone.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/339772/12205314
prj one_pulse_lcd.prj
`timescale 1ns/1ns
`include "ONE_PULSE_LCD.v"
`include "D:/Xilinx52/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/339772/12205332
sprj one_pulse_lcd.sprj
`timescale 1ns/1ns
`include "ONE_PULSE_LCD.v"
`include "D:/Xilinx52/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/252090/12303804
txt 新建 文本文档.txt
usart的verilog代码.rar
uart_vhdl.zip
sl811usb包含源程序.rar
mc8051_design.zip
mcpu_1[1].05.zip
minicpu.zip
mmc_lark_original.zip
www.eeworm.com/read/234547/14107037
qsf keyboardtest.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/127506/14351253
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fen_fen_test_v_tf is
end fen_fen_test_v_tf;
www.eeworm.com/read/228928/14357657
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity s_to_p_tb is
generic(
periode : integer := 25
);
end s_to_p_tb;
www.eeworm.com/read/228337/14391358
fld cpld_for_lcd.fld
E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd.quartus_db
cpld_for_lcd
www.eeworm.com/read/224733/14570346
qsf freq2.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu