phone.map.qmsg

卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 13 22:37:31 2006 " "Info: Processing started: Mon Mar 13 22:37:31 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off phone -c phone " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off phone -c phone" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "account1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file account1.v" { { "Info" "ISGN_ENTITY_NAME" "1 account1 " "Info: Found entity 1: account1" {  } { { "account1.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account1.v" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv " "Info: Found entity 1: clkdiv" {  } { { "clkdiv.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/clkdiv.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "account.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file account.v" { { "Info" "ISGN_ENTITY_NAME" "1 account " "Info: Found entity 1: account" {  } { { "account.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account.v" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "account_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file account_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 account_top " "Info: Found entity 1: account_top" {  } { { "account_top.bdf" "" { Schematic "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account_top.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "abc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file abc.v" { { "Info" "ISGN_ENTITY_NAME" "1 abc " "Info: Found entity 1: abc" {  } { { "abc.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/abc.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "account2.v(195) " "Warning: (10268) Verilog HDL information at account2.v(195): Always Construct contains both blocking and non-blocking assignments" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 195 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "account2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file account2.v" { { "Info" "ISGN_ENTITY_NAME" "1 account2 " "Info: Found entity 1: account2" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "p7segment_new.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file p7segment_new.v" { { "Info" "ISGN_ENTITY_NAME" "1 p7segment_new " "Info: Found entity 1: p7segment_new" {  } { { "p7segment_new.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/p7segment_new.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "account_top " "Info: Elaborating entity \"account_top\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "p7segment_new inst " "Warning: Block or symbol \"p7segment_new\" of instance \"inst\" overlaps another block or symbol" {  } { { "account_top.bdf" "" { Schematic "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account_top.bdf" { { 360 1184 1336 456 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "p7segment_new inst3 " "Warning: Block or symbol \"p7segment_new\" of instance \"inst3\" overlaps another block or symbol" {  } { { "account_top.bdf" "" { Schematic "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account_top.bdf" { { 592 1184 1336 688 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "account2 account2:inst2 " "Info: Elaborating entity \"account2\" for hierarchy \"account2:inst2\"" {  } { { "account_top.bdf" "inst2" { Schematic "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account_top.bdf" { { 520 736 952 712 "inst2" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "set_reg account2.v(33) " "Info: (10035) Verilog HDL or VHDL information at account2.v(33): object \"set_reg\" declared but not used" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "reset_ena account2.v(43) " "Info: (10035) Verilog HDL or VHDL information at account2.v(43): object \"reset_ena\" declared but not used" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 account2.v(49) " "Warning: Verilog HDL assignment warning at account2.v(49): truncated value with size 32 to match size of target (8)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(51) " "Warning: Verilog HDL assignment warning at account2.v(51): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 51 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(61) " "Warning: Verilog HDL assignment warning at account2.v(61): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 61 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(63) " "Warning: Verilog HDL assignment warning at account2.v(63): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(64) " "Warning: Verilog HDL assignment warning at account2.v(64): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 64 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(68) " "Warning: Verilog HDL assignment warning at account2.v(68): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 68 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(74) " "Warning: Verilog HDL assignment warning at account2.v(74): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 74 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(99) " "Warning: Verilog HDL assignment warning at account2.v(99): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 99 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(100) " "Warning: Verilog HDL assignment warning at account2.v(100): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 100 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(104) " "Warning: Verilog HDL assignment warning at account2.v(104): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 104 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(110) " "Warning: Verilog HDL assignment warning at account2.v(110): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(120) " "Warning: Verilog HDL assignment warning at account2.v(120): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 120 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(121) " "Warning: Verilog HDL assignment warning at account2.v(121): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 121 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(124) " "Warning: Verilog HDL assignment warning at account2.v(124): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 124 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(129) " "Warning: Verilog HDL assignment warning at account2.v(129): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 129 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(136) " "Warning: Verilog HDL assignment warning at account2.v(136): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(142) " "Warning: Verilog HDL assignment warning at account2.v(142): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(143) " "Warning: Verilog HDL assignment warning at account2.v(143): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 account2.v(155) " "Warning: Verilog HDL assignment warning at account2.v(155): truncated value with size 32 to match size of target (2)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 155 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(157) " "Warning: Verilog HDL assignment warning at account2.v(157): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 157 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 account2.v(158) " "Warning: Verilog HDL assignment warning at account2.v(158): truncated value with size 32 to match size of target (1)" {  } { { "account2.v" "" { Text "D:/老d/老师的任务/EDA/2005_experiment/2005_experiment/phone/account2.v" 158 0 0 } }  } 0}