代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11690391
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
Iz]gBl1MVeY1@Aca5DC9B23
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/apex20ke_atoms.v)
L0 1618
OV;L
www.eeworm.com/read/347114/11690403
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity dffe_io is
port(
\Q\ : out vl_logic;
\CLK\ : in vl_logic;
\ENA\ : in vl_logic;
www.eeworm.com/read/347114/11690513
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/347114/11690634
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
IbX`i3
VzNO3AF7X_1hjETK^b?5423
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratix_atoms.v)
L0 222
OV;L;5
www.eeworm.com/read/347114/11690777
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/347114/11690802
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
www.eeworm.com/read/347114/11690861
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
valt3pram
ITQezdiY7oBT6M>5
www.eeworm.com/read/347114/11690982
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
www.eeworm.com/read/347114/11691020
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_l22 is
port(
l22_out : out vl_logic;
a : in vl_logic;
b : in vl_l
www.eeworm.com/read/347114/11691096
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_l13 is
port(
l13_out : out vl_logic;
a : in vl_logic;
b : in vl_l