代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/410651/11273188
qsf ps2.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/410651/11273261
qmsg ps2.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/410650/11273434
qsf vga.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/409880/11308448
log stdout.log
License checkout: synplify_pc
Starting: D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1\bin\mbin\synplify.exe
Install: D:\Actel\Libero\Libero_v8.4\Synplify\synplify_94A1
Date: Th
www.eeworm.com/read/263082/11377262
qsf lab5.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/408281/11399996
qsf ps2.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/408281/11400024
qmsg ps2.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/405978/11452019
sft freq2_2.sft
set tool_name "ModelSim (Verilog)"
set corner_file_list {
{{"Slow Model"} {freq2_2.vo freq2_2_v.sdo}}
}
www.eeworm.com/read/400225/11580369
log stdout.log
Starting: C:\pasic\synplcty\bin\mbin\synplify.exe
Version: 7.0.2
Date: Fri Sep 13 17:34:10 2002
Running synthesis on demo_amba:Synthesis_and_SpDE_files
log file: "\\Judd_ql_dallas
www.eeworm.com/read/262354/11590898
tcl create_wtut_ver.tcl
# Tcl script to run in the Xilinx Tcl shell or the ISE Tcl Console
# To run this script, type "source create_vtut_ver.tcl"
# at Tcl prompt.
# set up the project
project new wtut_ver.ise
pr