代码搜索:Verilog

找到约 10,000 项符合「Verilog」的源代码

代码结果 10,000
www.eeworm.com/read/235010/14089077

mti ise_test.cr.mti

D:/Verilog/ise_test/params.v {1 {vlog -work work -novopt D:/Verilog/ise_test/params.v Model Technology ModelSim SE vlog 6.1f Compiler 2006.05 May 12 2006 } {} {}} D:/Verilog/ise_test/ddr_command.v
www.eeworm.com/read/204154/15343894

fld tiny16_maxii.fld

c:/otherquartusprojects/processor/verilog/tiny16/db/tiny16_MAXII.quartus_db tiny16_MAXII sgroom V1
www.eeworm.com/read/202736/15375130

rpt fcout.map.rpt

Analysis & Synthesis report for fcout Thu Apr 05 22:27:30 2007 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal N
www.eeworm.com/read/202015/15391096

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity and1 is port( y : out vl_logic; in1 : in vl_logic ); end and1;
www.eeworm.com/read/202015/15391111

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity stratix_asynch_lcell is generic( operation_mode : string := "normal"; sum_lutc_input : string := "datac"; lut_mask
www.eeworm.com/read/201251/15412135

tcl ddr_cntl_a_xmdf.tcl

# The package naming convention is _xmdf package provide ddr_cntl_a_xmdf 1.0 # This includes some utilities that support common XMDF operations package require utilities_xmdf # Define a
www.eeworm.com/read/102365/15784961

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity ddr_sdram_tb is port( ); end ddr_sdram_tb;
www.eeworm.com/read/290116/8503939

qsf de2_i2sound.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
www.eeworm.com/read/431720/8659880

rpt kit_de2.asm.rpt

Assembler report for kit_DE2 Sat May 31 20:22:41 2008 Version 6.0 Build 178 04/27/2006 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2
www.eeworm.com/read/387579/8664758

smsg den_lcm_test.map.smsg

Warning (10236): Verilog HDL Implicit Net warning at LCM_Display.v(103): created implicit net for "cheange_display_mode"