代码搜索：Verilog

找到约 10,000 项符合「Verilog」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/334413/12604013

qmsg uart_emitter.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/334413/12604109

qmsg usrt_receive.fit.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/334413/12604154

qmsg uart_emitter.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/334173/12623655

rpt colorbar.map.rpt

Analysis & Synthesis report for ColorBar Tue Sep 12 11:44:04 2006 Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version --------------------- ; Table of Contents ; -----------------
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www.eeworm.com/read/135714/13909182

npl uart_send.npl

JDF E // Created by ISE ver 1.0 PROJECT uart_send DESIGN uart_send Normal DEVKIT XC95108 PC84 DEVFAM xc9500 FLOW XST Verilog MODULE send.v MODSTYLE send Normal [STRATEGY-LIST] Normal=True,
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npl send.npl

JDF E // Created by ISE ver 1.0 PROJECT send DESIGN send Normal DEVKIT XC95108 PC84 DEVFAM xc9500 FLOW XST Verilog MODULE send.v MODSTYLE uart_send Normal [STRATEGY-LIST] Normal=True, 1038
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www.eeworm.com/read/135714/13909232

_prj send._prj

insert `timescale 1ns/1ns include include send.v include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
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_prj receive._prj

insert `timescale 1ns/1ns include include receive.v include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
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www.eeworm.com/read/135714/13909392

npl receive.npl

JDF E // Created by ISE ver 1.0 PROJECT receive DESIGN receive Normal DEVKIT XC95108 PC84 DEVFAM xc9500 FLOW XST Verilog MODULE receive.v MODSTYLE uart_rec Normal [STRATEGY-LIST] Normal=Tr
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www.eeworm.com/read/236762/14000081

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity pg4 is port( a : in vl_logic_vector(3 downto 0); b : in vl_logic_vector(3 downto 0); p
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