usrt_receive.fit.qmsg

Uart port 是一段不错的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 11 21:46:07 2006 " "Info: Processing started: Mon Dec 11 21:46:07 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off usrt_receive -c usrt_receive " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off usrt_receive -c usrt_receive" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "usrt_receive EP20K30ETC144-1 " "Info: Automatically selected device EP20K30ETC144-1 for design usrt_receive" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "clk automatically " "Info: Promoted cell \"clk\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "rest automatically " "Info: Promoted cell \"rest\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "Select~158 automatically " "Info: Promoted cell \"Select~158\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Mon Dec 11 2006 21:46:13 " "Info: Started fitting attempt 1 on Mon Dec 11 2006 at 21:46:13" {  } {  } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_PERFORMANCE_MAY_DEGRADE_AS_FDI_IS_NOT_LOADED" "" "Warning: Performance of this circuit may degrade because the Fitter Delay Information is not loaded." {  } {  } 0 0 "Performance of this circuit may degrade because the Fitter Delay Information is not loaded." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "1 " "Info: Overall column FastTrack interconnect = 1%" {  } {  } 0 0 "Overall column FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "2 " "Info: Overall row FastTrack interconnect = 2%" {  } {  } 0 0 "Overall row FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "1 " "Info: Maximum column FastTrack interconnect = 1%" {  } {  } 0 0 "Maximum column FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "10 " "Info: Maximum row FastTrack interconnect = 10%" {  } {  } 0 0 "Maximum row FastTrack interconnect = %1!d!%%" 0 0}  } {  } 0 0 "Design requires the following device routing resources:" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.728 ns register register " "Info: Estimated most critical path is register to register delay of 7.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns sample_counter\[2\]~reg0 1 REG LAB_10_D1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LAB_10_D1; Fanout = 5; REG Node = 'sample_counter\[2\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { sample_counter[2]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.890 ns) 1.297 ns rtl~0 2 COMB LAB_10_D1 8 " "Info: 2: + IC(0.246 ns) + CELL(0.890 ns) = 1.297 ns; Loc. = LAB_10_D1; Fanout = 8; COMB Node = 'rtl~0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.136 ns" { sample_counter[2]~reg0 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.406 ns) + CELL(0.890 ns) 4.593 ns inc_bit_counter~11 3 COMB LAB_7_A2 12 " "Info: 3: + IC(2.406 ns) + CELL(0.890 ns) = 4.593 ns; Loc. = LAB_7_A2; Fanout = 12; COMB Node = 'inc_bit_counter~11'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.296 ns" { rtl~0 inc_bit_counter~11 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(1.122 ns) 5.961 ns add~126 4 COMB LAB_6_A2 2 " "Info: 4: + IC(0.246 ns) + CELL(1.122 ns) = 5.961 ns; Loc. = LAB_6_A2; Fanout = 2; COMB Node = 'add~126'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.368 ns" { inc_bit_counter~11 add~126 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 6.076 ns add~122 5 COMB LAB_6_A2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.115 ns) = 6.076 ns; Loc. = LAB_6_A2; Fanout = 2; COMB Node = 'add~122'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.115 ns" { add~126 add~122 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 6.191 ns add~118 6 COMB LAB_6_A2 1 " "Info: 6: + IC(0.000 ns) + CELL(0.115 ns) = 6.191 ns; Loc. = LAB_6_A2; Fanout = 1; COMB Node = 'add~118'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.115 ns" { add~122 add~118 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.668 ns) 6.859 ns add~112 7 COMB LAB_6_A2 1 " "Info: 7: + IC(0.000 ns) + CELL(0.668 ns) = 6.859 ns; Loc. = LAB_6_A2; Fanout = 1; COMB Node = 'add~112'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.668 ns" { add~118 add~112 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.623 ns) 7.728 ns bit_counter\[3\]~reg0 8 REG LAB_6_A2 3 " "Info: 8: + IC(0.246 ns) + CELL(0.623 ns) = 7.728 ns; Loc. = LAB_6_A2; Fanout = 3; REG Node = 'bit_counter\[3\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.869 ns" { add~112 bit_counter[3]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.584 ns ( 59.32 % ) " "Info: Total cell delay = 4.584 ns ( 59.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.144 ns ( 40.68 % ) " "Info: Total interconnect delay = 3.144 ns ( 40.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "7.728 ns" { sample_counter[2]~reg0 rtl~0 inc_bit_counter~11 add~126 add~122 add~118 add~112 bit_counter[3]~reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 11 21:46:17 2006 " "Info: Processing ended: Mon Dec 11 21:46:17 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}